1. Field of the Invention
The present invention relates to LDMOS transistors and, more particularly, to a LDMOS transistor and a method of forming the LDMOS transistor with improved Rds*Cgd.
2. Description of the Related Art
A metal oxide semiconductor (MOS) transistor is a well-known semiconductor device that has a source, a drain, a body which has a channel region that lies between and touches the source and drain, and a gate that lies over and is isolated from the channel region by a gate dielectric layer. There are two types of MOS transistors: an NMOS transistor that has n+ source and drain regions with a p-type channel region, and a PMOS transistor that has p+ source and drain regions with an n-type channel region.
In operation, when the source and the body are grounded, a positive voltage is placed on the drain to set up a drain-to-source electric field, and a voltage is placed on the gate that is greater than a threshold voltage, a current flows from the drain to the source. When the voltage placed on the gate is less than the threshold voltage, such as when the gate is pulled down to ground, no current flows.
Current-generation MOS transistors are commonly used in low-voltage environments that range from, for example, 1.2V to 5V. In contrast, a high-voltage MOS transistor is a transistor that operates with voltages in the range of, for example, 10V to 400V. In order to handle the higher voltages, high-voltage MOS transistors are bigger than low-voltage MOS transistors.
One type of high-voltage MOS transistor is known as a laterally diffused MOS (LDMOS) transistor. LDMOS transistors are MOS transistors that also have a drain drift region. The drain drift region, which touches and lies between the drain and the channel region, has the same conductivity type as the drain, but a lower dopant concentration than the drain. In operation, the drain drift region reduces the magnitude of the drain-to-source electric field.
A new figure of merit (FOM) for high current (e.g., 10 A and above) and high frequency (1-10 MHz and higher) LDMOS transistors is Rds*Cgd, which is the product of the drain-to-source resistance (Rds) and the gate-to-drain capacitance (Cgd). To improve this FOM, it is desirable to reduce the Rds value, the Cgd value, or both of the values.
One approach to reducing Cgd is to use split or step gates in lieu of one gate. With step or split gates, a main gate and, for example, two progressively thinner gates are used so that the closer a gate lies to the drain region the thicker the underlying gate dielectric layer. One drawback to this approach, however, is that split or step gates are difficult and expensive to fabricate. In addition, split or step gates can require longer drain drift regions, which limit the device in high-speed mobile applications due to an increased Rds.